VHDL Codes

ALU

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-- Simple ALU Module (ESD book Figure 2.5)           

-- ALU stands for arithmetic logic unit.

-- It perform multiple operations according to 

-- the control bits.

-- we use 2's complement subtraction in this example

VHDL: Programming by Example

Douglas L.Perry, "VHDL: Programming by Example"


McGraw-Hill | ISBN: 0071400702 | 2002. | 497 p. | PDF | 1.73 MB

Perry teaches VHDL through a series of hundreds of practical, detailed examples, gradually increasing in complexity until youHeroturko??â"¢re capable of designing a fully functional CPU. The new Fourth Edition has been completely updated with all of the VDHL codes used in the examples changed to reflect todayHeroturko??â"¢s faster and more efficient design methods.






DownloadLink:

http://rapidshare.com/files/102960842/VHDL.Programming.by.Example.4th.Ed.rar

VHDL samples

The sample VHDL code contained below is for tutorial purposes.
An expert may be bothered by some of the wording of the examples
because this WEB page is intended for people just starting to
learn the VHDL language. There is no intention of teaching
logic design, synthesis or designing integrated circuits.
It is hoped that people who become knowledgeable of VHDL will
be able to develop better models and more rapidly meet whatever
their objectives might be using VHDL simulations.

VHDL Examples

So, they've told you that you need to design this thing called an FPGA (or ASIC) with this thing called VHDL. Where do you start?

VHDL is just a programming language, pretty much like any other, with it's own funkie syntax. However, VHDL is a bit different because it tries to emulate hardware. Thus, VHDL needs to capability to let several things happen at the same time.

The main thing you need to worry about when programming in VHDL is the concept of "delta time". Lets take the following example:

A <= B and C;

If "B" changes the "A" changes one "delta" cycle later. A "delta" takes ZERO ns to actually happen, but there IS a delay there. Thus you need to worry about osscilations if you have any asynchronous feedback.

The following code was put together using the 1076.3 (numeric_std) packages to represent synthesizable arithmetic.

Basic Logic Gates [driver]

Behavior Code

---------------------------------------
-- driver (ESD book figure 2.3)
--
-- two descriptions provided
----------------------------------------

library ieee;
use ieee.std_logic_1164.all;

----------------------------------------

entity Driver is
port( x: in std_logic;
F: out std_logic
);
end Driver;

----------------------------------------

architecture behv1 of Driver is
begin

process(x)
begin
-- compare to truth table
if (x='1') then
F <= '1';
else
F <= '0';
end if;
end process;

end behv1;

architecture behv2 of Driver is
begin

F <= x;

end behv2;

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