Monday, June 28, 2010

VHDL Codes


ALU


---------------------------------------------------


-- Simple ALU Module (ESD book Figure 2.5)


-- ALU stands for arithmetic logic unit.


-- It perform multiple operations according to


-- the control bits.


-- we use 2's complement subtraction in this example



-- two 2-bit inputs & carry-bit ignored


---------------------------------------------------






library ieee;


use ieee.std_logic_1164.all;


use ieee.std_logic_unsigned.all;


use ieee.std_logic_arith.all;





---------------------------------------------------





entity ALU is





port( A: in std_logic_vector(1 downto 0);


B: in std_logic_vector(1 downto 0);


Sel: in std_logic_vector(1 downto 0);


Res: out std_logic_vector(1 downto 0)


);





end ALU;





---------------------------------------------------





architecture behv of ALU is


begin





process(A,B,Sel)


begin





-- use case statement to achieve


-- different operations of ALU





case Sel is


when "00" =>


Res <= A + B;


when "01" =>


Res <= A + (not B) + 1;


when "10" =>


Res <= A and B;


when "11" =>


Res <= A or B;


when others =>


Res <= "XX";


end case;





end process;





end behv;














RAM MODULE








-- a simple 4*4 RAM module (ESD book Chapter 5)


-- KEYWORD: array, concurrent processes, generic, conv_integer


--------------------------------------------------------------





library ieee;


use ieee.std_logic_1164.all;


use ieee.std_logic_arith.all;


use ieee.std_logic_unsigned.all;





--------------------------------------------------------------





entity SRAM is


generic( width: integer:=4;


depth: integer:=4;


addr: integer:=2);


port( Clock: in std_logic;


Enable: in std_logic;


Read: in std_logic;


Write: in std_logic;


Read_Addr: in std_logic_vector(addr-1 downto 0);


Write_Addr: in std_logic_vector(addr-1 downto 0);


Data_in: in std_logic_vector(width-1 downto 0);


Data_out: out std_logic_vector(width-1 downto 0)


);


end SRAM;





--------------------------------------------------------------





architecture behav of SRAM is





-- use array to define the bunch of internal temparary signals





type ram_type is array (0 to depth-1) of


std_logic_vector(width-1 downto 0);


signal tmp_ram: ram_type;





begin





-- Read Functional Section


process(Clock, Read)


begin


if (Clock'event and Clock='1') then


if Enable='1' then


if Read='1' then


-- buildin function conv_integer change the type


-- from std_logic_vector to integer


Data_out <= tmp_ram(conv_integer(Read_Addr));


else


Data_out <= (Data_out'range => 'Z');


end if;


end if;


end if;


end process;





-- Write Functional Section


process(Clock, Write)


begin


if (Clock'event and Clock='1') then


if Enable='1' then


if Write='1' then


tmp_ram(conv_integer(Write_Addr)) <= Data_in;


end if;


end if;


end if;


end process;





end behav;





ROM MODULE





-- 32*8 ROM module (ESD Book Chapter 5)


-- ROM model has predefined content for read only purpose


--------------------------------------------------------------





library ieee;


use ieee.std_logic_1164.all;


use ieee.std_logic_arith.all;


use ieee.std_logic_unsigned.all;





entity ROM is


port( Clock : in std_logic;


Reset : in std_logic;


Enable : in std_logic;


Read : in std_logic;


Address : in std_logic_vector(4 downto 0);


Data_out: out std_logic_vector(7 downto 0)


);


end ROM;





--------------------------------------------------------------





architecture Behav of ROM is





type ROM_Array is array (0 to 31)


of std_logic_vector(7 downto 0);





constant Content: ROM_Array := (


0 => "00000001", -- Suppose ROM has


1 => "00000010", -- prestored value


2 => "00000011", -- like this table


3 => "00000100", --


4 => "00000101", --


5 => "00000110", --


6 => "00000111", --


7 => "00001000", --


8 => "00001001", --


9 => "00001010", --


10 => "00001011", --


11 => "00001100", --


12 => "00001101", --


13 => "00001110", --


14 => "00001111", --


OTHERS => "11111111" --


);





begin


process(Clock, Reset, Read, Address)


begin


if( Reset = '1' ) then


Data_out <= "ZZZZZZZZ";


elsif( Clock'event and Clock = '1' ) then


if Enable = '1' then


if( Read = '1' ) then


Data_out <= Content(conv_integer(Address));


else


Data_out <= "ZZZZZZZZ";


end if;


end if;


end if;


end process;


end Behav;








GCD CALCULATOR


-- Behvaior Design of GCD calculator


----------------------------------------------------


library ieee;


use ieee.std_logic_1164.all;


use ieee.std_logic_arith.all;


use work.all;


-----------------------------------------------------


entity gcd1 is


port( Data_X: in unsigned(3 downto 0);


Data_Y: in unsigned(3 downto 0);


Data_out: out unsigned(3 downto 0)


);


end gcd1;





architecture behv of gcd1 is


begin


process(Data_X, Data_Y)


variable tmp_X, tmp_Y: unsigned(3 downto 0);


begin


tmp_X := Data_X;


tmp_Y := Data_Y;





for i in 0 to 15 loop


if (tmp_X/=tmp_Y) then


if (tmp_X < tmp_Y) then


tmp_Y := tmp_Y - tmp_X;


else


tmp_X := tmp_X - tmp_Y;


end if;


else


Data_out <= tmp_X;


end if;


end loop;





end process;


end behv;





FSM CODE


-- GCD design using FSMD (ESD book Figure 2.9)


-- GCD algorithm behavior modeling (GCD.vhd)


-- the calculator has two 4-bit inputs and one output


--


-- NOTE: idle state required to obtain


-- the correct synthesis results


--------------------------------------------------------------





library ieee;


use ieee.std_logic_1164.all;


use ieee.std_logic_arith.all;


use work.all;





--------------------------------------------------------------





entity gcd is





port( clk: in std_logic;


rst: in std_logic;


go_i: in std_logic;


x_i: in unsigned(3 downto 0);


y_i: in unsigned(3 downto 0);


d_o: out unsigned(3 downto 0)


);


end gcd;





--------------------------------------------------------------





architecture FSMD of gcd is


begin





process(rst, clk)





-- define states using variable


type S_Type is (ST0, ST1, ST2);


variable State: S_Type := ST0 ;


variable Data_X, Data_Y: unsigned(3 downto 0);





begin





if (rst='1') then -- initialization


d_o <= "0000";


State := ST0;


elsif (clk'event and clk='1') then


case State is


when ST0 => -- starting


if (go_i='1') then


Data_X := x_i;


Data_Y := y_i;


State := ST1;


else


State := ST0;


end if;


when ST1 => -- idle state


State := ST2;


when ST2 => -- computation


if (Data_X/=Data_Y) then


if (Data_X<Data_Y) then


Data_Y := Data_Y - Data_X;


else


Data_X := Data_X - Data_Y;


end if;


State := ST1;


else


d_o <=Data_X; -- done


State := ST0;


end if;


when others => -- go back


d_o <= "ZZZZ";


State := ST0;


end case;


end if;





end process;





end FSMD;

























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