Monday, June 28, 2010

VHDL Examples

So, they've told you that you need to design this thing called an FPGA (or ASIC) with this thing called VHDL. Where do you start?

VHDL is just a programming language, pretty much like any other, with it's own funkie syntax. However, VHDL is a bit different because it tries to emulate hardware. Thus, VHDL needs to capability to let several things happen at the same time.

The main thing you need to worry about when programming in VHDL is the concept of "delta time". Lets take the following example:

A <= B and C;

If "B" changes the "A" changes one "delta" cycle later. A "delta" takes ZERO ns to actually happen, but there IS a delay there. Thus you need to worry about osscilations if you have any asynchronous feedback.

The following code was put together using the 1076.3 (numeric_std) packages to represent synthesizable arithmetic.

  • A few lessons learned when it comes to writing VHDL code:

  • Complete your sensativity list in process statments. If a process statment is not a clocked process, then EVERY input used in that process statment needs to be in the sensativity list.

  • Reset ALL signals in your in a clocked process statment, or NONE. If you don't want a reset on a signal, put it in a seperate process statment, or reset it to an '-'.

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